DVB-ASI Burst Transmitter

This is really for the sake of completeness. Since I talked about SMPTE-310M — even though there isn't much to it — I might as well cover the other MPEG-2 transport interface: European Standard EN 50083-9, Annex B, also known as DVB-ASI.

Xilinx has their XAPP514, and Altera has their ASI MegaCore Function, but sometimes you think you can do better, you know? I actually probably can't, but at the very least you might have no need for test streams, nor would you require a full implementation of the 8B/10B encoder.

Discussion of the system after the RTL listing.

The RTL

Burst Transfer Mode

There are two transmission modes: continuous/interleaved and packet/burst. You can take a look at the standard if interested, but the gist of it is you can either transmit the entire packet at once, or alternate data with K28.5 stuffing characters. Packet burst mode means using a larger FIFO because more of the packet has to be buffered, but on the other hand, burst mode would result in a higher maximum throughput. The other trade off is that there is increased latency while you wait for packet data to accumulate in the FIFO.

Still, I like the prospect of higher throughput, and the additional hardware cost is minimal. Suppose you choose to wait until a full packet is buffered in a FIFO before transmitting just to be safe, like I did. How large of a FIFO do you really need? Surely 256x8-bits at the most, if you're really that scared of the FIFO overflowing. Such a FIFO would comfortably fit into a single Altera M4K block.

Data Input

The FIFO is assumed to place data at the output immediately, and the read request flag is thus used as a data acknowledge. For Altera, that mode of operation is called Show Ahead mode. For Xilinx, it's First Word Fall Through.

The FIFO is implementation dependent and the RTL can be simplified a bit if the FIFO primitive supports programmable thresholding. If you take a look at the state machine controller architecture, you'll see that I included a FIFO read counter comparison. You might be able to save some logic if you rip that out and use a FIFO threshold flag when using a FIFO wizard. That is, unless the FIFO wizard you're using goes and implements that thresholding in user logic.

Minimal 8B/10B Encoder

The only command character ever used by DVB-ASI is the K28.5 null character for link stuffing. I encapsulated the data character encoder into a giant ROM, which may or may not be so giant by today's standards. This seems like a waste, given that the creators had a more compact solution, but the reality is that even Xilinx implements their 8B/10B encoder using a large lookup table.

Check out the following block diagram (open it in another window if necessary). I registered the inputs and outputs of the ROM out of practice which meant having to pipeline the valid signal. If you so choose you can probably save a flip-flop or two without violating timing constraints on the 27 MHz clock.

Partial 8B/10B encoder block diagramPartial 8B/10B encoder block diagram

These days, RAM on FPGA's is plentiful. Just have the synthesis tool pack everything into a single Block RAM and move along. Even a Cyclone III will hold this ROM, at 5,376 bits, in a single M9K RAM, of which the lowest end variant has 46.

If you're curious, Annex C of the DVB-ASI specification has a table of all the command and data character mappings. I actually used an 8B/10B application note provided by Actel. No, I did not go through all 256 entries by hand, but I did have to write myself a little text processing program, in conjunction with copious copy and paste.

The Actel chart is useful because in addition to accounting for certain special cases in the bit patterns based on disparity, it has a column indicating whether or not the disparity has to be inverted. That makes 256 addresses each resolving to 21 bits, hence the 5,376 bit total.

State Machine Controller

Notice that the state machine controller will automatically insert at least two K28.5 characters before the start of every packet. This is in keeping with the standard.

The packet counter is assuming a packet length of 188 bytes. Apparently 204 byte packets are also acceptable, which might contain forward error correction information. Adjust as necessary.

In theory, the link is always running. From the moment the system powers on, K28.5 characters are being fired off to help the receiver synchronize its data recovery circuits. If you want to switch the transmitter on and off, insert clock enables.

The 10-bit output is registered inside the encoder block, so I didn't bother to register it again. The data acknowledge signaling and the rest should be pretty self-explanatory.

Passing the Buck: FPGA Implementation Options

For FPGA users, there's no escaping the need for a high-speed cable driver. Xilinx's XAPP514 has a reference implementation using the CLC001 on page 419, Figure 15-21.

Serialization will depend on what kind of FPGA you have. Xilinx Virtex-4 and better FPGA's have two OSERDES blocks per differential IOB that can be used in a master-slave configuration to form a 10-bit serializer. What's nice about this is that you only have to feed a 135 MHz clock and use DDR mode. The master and slave OSERDES must be placed together in a single differential pair site, so you will have to take this into consideration when doing board design. Try to get the OSERDES configuration to place and route successfully before finalizing the board layout.

Altera users will be pleased to know that Quartus II will build you a 10-bit serializer, clock multiplication and all. Use the alt_lvds MegaFunction.

For other Xilinx parts, it looks like serialization will have to be performed using a shift register in general logic fabric, as there are no hard serializer blocks and I'm not aware of a serializer wizard in Core Generator. If your part isn't ancient and has DDR IOB's, the OSERDES can be replicated by using a counter (controls the load signal) and two 5-bit shift registers running at 135 MHz to feed the two DDR flip-flops, one triggered by the positive edge of the clock, and the other by the negative edge. A small, 2x10-bit FIFO would be useful to isolate the 27 MHz and 135 MHz clock domains. If you are without DDR, you'll have to take your chances with a 270 MHz 10-bit shift register with the requisite load control logic.

High speed I/O requires transmission line termination consideration. Check your FPGA manual for termination schemes, if necessary. For example the Cyclone III sports on-chip source termination for some differential pairs, and requires off-chip termination for others. Others may not have any on-chip source termination.

Further Reading

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